Job Responsibilities

1. Develop and establish validation strategies and plans, perform test function point decomposition, and set up simulation validation environments.

2. Responsible for chip system-level/module-level verification, ensuring verification quality.

3. Develop reference models and test vectors, conduct regression testing, assist in debugging and verification.

Qualification for the position

1. Proficient in using verification languages such as Verilog/SystemVerilog.

2. Familiar with UVM verification methodology, has experience in building UVM verification environments.

3. Experience in system-level/module-level verification is preferred.

4. Proficient in writing automation test scripts using scripting languages.